The microelectronic components in a semiconductor device such as an integrated circuit (IC) or a discrete device can easily be damaged by forces in the harsh external world. Some sort of packaging material is normally placed around the electronic components to protect them from the outside environment. The packaging material must, however, be situated on the device in such a way that the material does not in itself cause the components to fail.
Some of the problems that arise in placement of the packaging material can be understood with reference to FIGS. 1a-1f which illustrate the final stages in the fabrication, including the packaging, of a group of conventional IC's. The starting point for making the IC's is a semiconductor wafer containing a number of dice.
At the stage indicated in FIG. 1a, the wafer consists of a monocrystaline silicon semiconductive substrate 10, a group of electrical interconnection systems 12, one for each die, and an electrically insulating layer 14 of a passivating material such as phosphosilicate glass or silicon nitride. Various N-type and P-type regions (not shown in the drawings) exist in substrate 10. Each interconnection system 12 consists of a set of electrical lines and insulators formed on substrate 10. The lines are selectively connected to the N-type and P-type regions. Items 16 in systems 12 are the metallic bond pads, typically consisting of an aluminum alloy, through which the dice electrically communicate with the outside world. Insulating layer 14 overlies systems 12 and extends down to substrate 10 at the intended locations 18 for the side boundaries of the portions of substrate 10 used in the various IC's. More particularly, locations 18 which laterally circumscribe each system 12, are the places where the wafer is later cut into separate dice.
Before going further, a comment needs to be made about lithographic terminology. Material is "actinic" if it can be formed into a lithographic pattern by selectively exposing portions of a layer of the material to radiation that causes the exposed portions to change their chemical structure and subsequently developing the layer to remove either the exposed portions or the unexposed portions. Actinic material such as photoresist is negative "tone" when the exposed portions (of changed chemical structure) remain after development. The "tone" is positive if the unexposed portions remain after development.
Turning back to FIGS. 1a-1f, a blanket masking layer 20 of photoresist is formed on layer 14 as shown in FIG. 1b. Photoresist layer 20 is selectively exposed to ultraviolet (UV) light through a radiation mask 22. If, for example, the tone of the photoresist is negative, mask 22 has opaque areas that prevent UV light from impinging on parts of layer 20 lying above bond pads 16 and locations 18. After developing layer 20 to remove the unexposed photoresist, layer 14 is etched through the resulting apertures in layer 20 to form bond pad openings 24 and scribe line openings 26 that respectively extend down to pads 16 and locations 18. The remaining photoresist is removed to produce the structure depicted in FIG. 1c.
Next, substrate 10 is scribed along locations 18 to break the wafer into the separate dice, one for each IC. FIG. 1d illustrates one of the resulting dice. The portion of substrate 10 used in the die of FIG. 1d is indicated as semiconductive body 28.
Concentrating on this particular die, body 28 is mounted on the central section 30 of a metallic lead frame having a set of leads 32 separate from section 30. See FIG. 1e. Leads 30 are connected respectively to pads 16 by way of gold wires 34. The combination of leads 32 and wires 34 forms a set of electrical conductors that connect system 12 with the external world. At the place where each wire 34 is bonded to its pad 16 in its opening 24, wire 34 spreads out into a deformed "ball" 36.
The die can now be packaged in various ways. In one packaging technique investigated in the prior art, a small amount of a liquid such as a silicone is deposited on top of the die and then suitably treated to form an electrically insulating elastomeric (or rubbery) layer 38. See FIG. 1f. Layer 38 typically has a glass transition temperature of about -100.degree. C. Portions of elastomeric layer 38 normally "wick up" slightly over balls 36. The resulting structure is encapsulated with a package coating 40 of a hard electrically insulating material in such a way that only a part of each lead 32 protrudes through coating 40.
Coating 40 typically consists of an epoxy or other thermosetting resin molded around the die and lead frame at an elevated temperature. During the subsequent cooldown to room temperature, coating 40 shrinks much more than the die and lead frame. Layer 38 relieves much of the severe mechanical stress that would otherwise be placed on body 28 and interconnection system 12 as a result of the cooldown shrinkage.
The IC is now subjected to accelerated life tests to assess how it will perform. The tests typically entail cycling the IC rapidly between the industry-standard limits of -65.degree. C. and 150.degree. C. in both an air environment and a liquid environment.
A major difficulty with the IC of FIG. 1f centers around the part of each wire 34 where the top of layer 38 adjoins coating 40 just above associated ball 36. During the life tests, this part of wire 34 often breaks after a small number of thermal cycles, resulting in IC failure. The breakage mechanism appears to be fatigue produced by large differential thermal expansions/contractions in the IC that cause the portion of wire 34 in coating 40 to be shifted back and forth relative to the portion of wire 34 in layer 38.
Eliminating stress-relief layer 38 shifts the area of high stress down to balls 36. Because the area of each ball 36 where it contacts its pad 16 is much greater, typically at least four times greater, than the cross-sectional area of the remainder of its wire 34, ball 36 rarely breaks if layer 38 is absent. At the worst, ball 36 moves slightly. This is usually not catastrophic since ball 36 normally remains in contact with pad 16. However, the electronic components in interconnection system 28 and substrate 12 are now subjected to high stress during the thermal cycling and can fail unduly rapidly. It would be desirable to have a mechanism that avoids placing substantial stress on system 28 and substrate 12 without causing wires 34 to break.